1. Field of the Invention
The present invention relates to a device and method for driving a matrix type liquid crystal display apparatus, capable of improving the display quality thereof.
2. Description of the Related Art
A configuration for driving a typical simple matrix type liquid crystal display panel of a prior art is shown in FIG. 68. A liquid crystal panel 251 is connected with a segment side drive circuit 252 which is a segment driver and with a common side drive circuit 253 which is a common driver. The segment side drive circuit 252 and the common side drive circuit 253 are connected with a power circuit 254 which supplies electric power and a controller 255 which sends various control signals. The controller 255 supplies the segment side drive circuit 252 with display data, data latch clock for taking in the display data, horizontal synchronization signal and AC-converting signal for alternately driving the liquid crystal panel 251. The controller 255 supplies the common side drive circuit 253 with a horizontal synchronization signal, an AC-converting signal and a vertical synchronization signal for recognizing the start point of one screen. The power circuit 254 generates six voltages V0, V1, V2, V3, V4 and V5, having voltage levels increasing in this order, respectively, and supplies voltages V0, V2, V3, and V5 to the segment side drive circuit 252, and voltages V0, V1, V4 and V5 to the common side drive circuit 253. The liquid crystal panel 251 includes segment electrodes X1, X2, X3, X4, . . . , Xm and common electrodes Y1, Y2, Y3, Y4, . . . . , Yn which constitute a simple matrix while a liquid crystal cell located at the intersection of a segment electrode and a common electrode forms a pixel.
FIG. 69 shows an internal configuration of the segment side drive circuit 252. The segment side drive circuit 252 includes a shift register 261, a data latch 262, a line latch 263, a level shifter 264 and a liquid crystal drive output circuit 265, and is capable of driving, for example, 160 columns of segment electrodes. Display data for 160 columns is serially inputted to the shift register 261 in synchronization with data latch clock, thereby to be converted to parallel data in the shift register 261 and is latched and stored in the data latch 262. When an amount of data corresponding to one scan electrode has been accumulated, horizontal synchronization signal (LP) is added while the stored display data is latched in the line latch 263 then subjected to level shift in the level shifter 264, and is sent to the liquid crystal drive output circuit 265. The level shifter 264 converts the voltage levels of ordinary logic circuits such as the shift register 261, the data latch 262 and the line latch 263 to liquid crystal drive voltage level of the liquid crystal drive output circuit 265. The liquid crystal drive output circuit 265 outputs an output voltage for driving the segment electrodes of the liquid crystal panel 251 in accordance to an input supplied from the level shifter 264 and to the AC-converting signal.
FIG. 70 shows the operation of the prior art shown in FIG. 68. Although description that follows assumes that the liquid crystal panel 251 has seven scan electrodes for the convenience of description, actual liquid crystal panel 251 has greater number of scan electrodes. Common output voltage VY for the common electrodes which are scan electrodes successively selects, in accordance to the horizontal synchronization signal, the scanning lines to be displayed starting with the top line based on the vertical synchronization signal. For the common output voltage VY, one level is selected from among the four power voltages V0, V1, V4 and V5 according to a combination of the horizontal synchronization signal and the AC-converting signal, and is applied to the common side electrodes. As the segment output voltage VX for the segment electrodes which are data electrodes, one level is selected from among four liquid crystal drive power voltages V0, V2, V3, and V5 in accordance to the display data, while outputs for one scan electrode are applied in parallel to the segment side electrodes.
In the liquid crystal panel 251, potential difference between the segment side electrode and the common side electrode is applied to each pixel, while whether to display or not is determined according to the effective value of the potential difference over one frame period which is the time required to display one image frame. In the liquid crystal panel 251, there occur slight differences in the display color and the display density on the panel between a portion where identical display, for example ON display or OFF display, is given over the entire area and a portion where ON display and OFF display are repeated alternately every other line to give stripe display, for example, even when comparison is made between the ON display portions or between the OFF display portions.
(1) Assume a case of ON display given uniformly over the entire screen, then segment output voltage VXA from each segment side drive circuit 252 takes only either one of V0 and V5 which are ON display voltage levels, according to a combination with the AC-converting signal, to be output during one frame period, as shown in FIG. 71. Effective value Veff1 of voltage VA which is applied to a liquid crystal cell constituting each pixel of the liquid crystal panel 251 is given in terms of the difference of the segment output waveform and common output waveform.
(2) Assume a case of stripe display where display data alternately repeat ON and OFF on every other scanning line, then output waveform of the segment side drive circuit 252 alternately takes V0, V5 levels which are ON display voltage levels or V2, V3 levels which are OFF display voltage levels according to a combination with the AC-converting signal during one frame period, as shown in FIG. 72. Voltage VB which is applied to a liquid crystal cell is given in terms of the effective voltage Veff2 which is the difference of the segment output waveform and the common output waveform.
Difference between the cases (1) and (2) is that the frequency of changes in the output level of the segment output waveform is different. When the output level changes, output waveform is rounded due to capacitance of the liquid crystal cell, electrical resistance of the electrodes of the liquid crystal panel, output resistance of the drive circuit and other factors, and therefore a high frequency of changes causes the effective voltage to decrease. Frequency of changes in the output level of the segment output waveform in FIG. 71, for example, is less than the frequency of changes in the segment output waveform in FIG. 72 by 12 in one frame period. Let S represent the loss in the effective voltage applied to the liquid crystal cell due to rounding of the waveform caused in one change, then the effective voltage of the liquid crystal cell shown in FIG. 71 becomes higher by an amount corresponding to 12S than the effective voltage of the liquid crystal cell of FIG. 72. Consequently, Veff1 becomes greater than Veff2 (Veff1&gt;Veff2) even for pixels of the same ON display, resulting in an unevenness in luminance called shadowing. When an output waveform of each drive circuit in the case of OFF display over the entire screen is considered, then the output waveform of the segment side drive circuit takes only either one of V2 and V3 during one frame period. Effective voltage Veff3 of voltage VC which is applied to a liquid crystal cell is given in terms of the difference of segment output waveform and common output waveform as shown in FIG. 73. When an output waveform of each drive circuit for OFF display in the case of stripe display is considered, segment output waveform alternately takes V0, V2 level or V3, V5 level upon every horizontal synchronization signal during one frame period, and is represented by effective voltage Veff4 of voltage VD which is applied to a liquid crystal cell as shown in FIG. 74. Similarly to the difference in the segment waveform during ON display, the effective voltages are related as Veff3&gt;Veff4 also during OFF display, resulting in unevenness in luminance.
Prior art for reducing the unevenness in luminance of display which depends on the display pattern in a liquid crystal display apparatus where a simple matrix type liquid crystal panel is driven is disclosed, for example, in the Japanese Unexamined Patent Publication JP-A 5-265402 (1993) Publication. This prior art provides a method for driving the simple matrix type liquid crystal display apparatus wherein a correction period is provided for all outputs from column side drive circuit, which corresponds to the segment side drive circuit, in every period of scanning one line. In the correction period, instead of display voltage which is output from the column side drive circuit, a corrected voltage is output which is an intermediate voltage level between the ON display voltage level and the OFF display voltage level.
FIG. 75 shows a configuration for driving a liquid crystal panel according to prior art disclosed in the Japanese Unexamined Patent Publication JP-A 5-265402 (1993). Voltages V0 through V5 which are output from a power supply circuit 254 are given via a voltage selector 271 as VS1 through VS4 to a column side drive circuit 272 which drives segment electrodes of the liquid crystal panel 251. A row side drive circuit 273 which drives the common electrodes receives four voltages V0, V1, V4 and V5 similarly to the configuration shown in FIG. 68. Operation of the voltage selector 271 is switched according to the level of correction clock which is output by a counter 274 that counts the data latch clock and the horizontal synchronization signal.
FIGS. 76, 77 and 78 show the common output voltage VY and the segment output voltage VXm in the cases of stripe display, OFF display over the entire screen and ON display over the entire screen, respectively. Because the output waveforms of all segment side drive circuits change to the intermediate voltage level between the ON display voltage level and the OFF display voltage level for every scanning period regardless of the display pattern, frequencies of changes in the outputs of the segment side drive circuits become identical, thus variation in the effective voltage of the applied voltage which depends on the display pattern is reduced.
FIG. 79 shows the output waveform according to a technology proposed in the Japanese Patent Application No.7-89860 filed by the present applicant. This technology makes it possible to drive the segment side drive circuit with a low power voltage, for example a single power voltage of 5V. The segment side drive circuit outputs one of two voltages VSH and VSL in accordance to a combination of AC-converting signal and display data, thereby to determine whether the display is to be ON or OFF. The common side drive circuit selects one voltage from among three voltages VCH, VCM and VCL according to a combination of AC-converting signal and selection or non-selection, and outputs the selected voltage.
Comparison of FIG. 70 and FIG. 79 shows that the waveform applied to the liquid crystal cell is the same for both drive methods. Effective value of the applied voltage also becomes the same, provided the following equations hold. This method of driving will be called the 5V drive method. EQU V0-V5=VCH-VSL EQU V0-V4=VCH-VSM EQU V0-V3=VCH-VSH EQU (V4-V4=V1-V1)=(VCM-VSM)=0 EQU (V4-V5, V1-V2)=VCM-VSL EQU (V4-V3, V1-V0)=VCM-VSH EQU V5-V2=VCL-VSL EQU V5-V1=VCL-VSM EQU V5-V0=VCL-VSH
However, even when the 5V drive method is employed, there is a possibility of luminance unevenness to occur due to the difference in the frequency of changes in the output level of the segment output waveform, similar to the prior art described previously. When the prior art disclosed in the Japanese Unexamined Patent Publication JP-A 5-265402 (1993) Publication is applied, frequency of changes in the output level of the segment side drive circuit becomes the same regardless of the display pattern and therefore variation in the applied voltage which depends on the display pattern can be mitigated. A timing chart in this case is shown in FIG. 80.
The present applicant also proposed a technology as the Japanese Patent Application No. 7-128008 where luminance unevenness is reduced by reversing the output of display data in periods when the correction clock is high, in case where the same display is given over consecutive scanning periods.
Shadowing may result from other causes as shown in FIGS. 81, 82, 83 and 84, where changes in the output waveform to the segment electrodes cause voltage variations in the common electrodes as spike noise, which may result in changes in the effective value of the voltage applied to the liquid crystal cell. This is because the segment electrodes and the common electrodes which constitute the liquid crystal panel have non-zero electric resistance and the liquid crystal layer existing between the electrodes acts as a dielectric material. FIG. 81 shows a case when the same drive method as that of the prior art shown in FIG. 68 and FIG. 75 is employed, and FIGS. 82 through 84 show timing charts in case where the 5V drive method similar to that of FIG. 79 is employed.
In the prior art disclosed in the Japanese Unexamined Patent Publication JP-A 5-265402 (1993), correction periods are provided for all drive waveforms of the segment electrodes thereby to output an intermediate voltage level between ON display voltage level and OFF display voltage level, and therefore the effective voltage applied to the liquid crystal cell changes the same number of times regardless of the display pattern, making it possible to eliminate the luminance unevenness due to rounding of the waveform caused by the change. However, because the intermediate level is output during the correction period, effective voltage becomes lower than the effective voltage applied to the liquid crystal cell in the case of ordinary drive method. Thus there arises such a problem that the contrast decreases as the result of decreasing effective voltage leading to lower display quality. That is, as shown in FIG. 85, effective value Veffm of voltage Vm applied to the liquid crystal cell decreases because the portion indicated by hatching is lost. To avoid degradation of the display quality due to such a loss of the effective voltage, it is necessary to have a higher bias ratio and increase the difference between the ON display voltage level and the OFF display voltage level. When bias ratio is increased, magnitude of change in the output voltage increases and an increase in current consumption due to the change in the display voltage level causes the power consumption to increase.
The technology proposed by the present applicant, which reduces the luminance unevenness by reversing the white and black of display data in the correction period in the case of same display, causes an increase in current consumption due to greater voltage changes, because voltage change is caused to occur between ON and OFF. Although it is necessary to decrease the pulse width of the correction clock in order to make optimum correction because of the greater voltage changes in the correction period, it is difficult to make such an adjustment. Also there is such a problem that the loss in the effective voltage applied to the liquid crystal cell is significant thus leading to degradation of the display quality, as described previously.
Today, liquid crystal panels of simple matrix type and active matrix type are required to give color display on larger screens at higher speed with lower voltage, and particularly they are required to be capable of effectively eliminating luminance unevenness and achieving low-voltage drive.